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XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
3.2 DETAILED REGISTERS DESCRIPTIONS
REV. 1.0.0
A DDRESS
0x00
REGISTER NAME
READ_SUBADDRESS
DESCRIPTION
b[7:0]
T YPE
R/W
To ease reading via I2C, the data of READ_SUBADDRESS is a
pointer to the first address in the I2C memory map. If the master
wants to read the content of register e.g. 0x2E, the master first
need to write 0x2E to READ_SUBADDRESS.
0x01
RX_FIFO
b[7:0]
R
To retrieve data from the RX Data Buffer, the master must read
from this register. All entries of the RX Data Buffer are mapped to
this register, offering a FIFO mechanism.
0x02
TX_FIFO
b[7:0]
W
To put data into the TX Data Buffer, the master must write to this
register. All entries of the TX Data Buffer are mapped to this regis-
ter, offering a FIFO mechanism.
0x03
FIFO_CONTROL
b[2:0] = 001 --> reset RX_FIFO read address
R/W
b[2:0] = 010 --> reset RX_FIFO write address
b[2:0] = 011 --> reset TX_FIFO read address
b[2:0] = 100 --> reset TX_FIFO write address
b[2:0] = 101 --> reset RX_FIFO read address
b[2:0] = 110 --> reset RX_FIFO write address
b[2:0] = 001 --> reset RX_FIFO read address
b[2:0] = 111 --> reset all RX and TX FIFO addresses
b[7:3] not used
Via this register, the internal FIFO read and write pointers of the TX
Data Buffer and the RX Data Buffer can be set to 0X00. The con-
tent of the Data Buffers is unaffected by resetting the pointers.
0x04
INT_MASKING
b[0] = 0 --> pck_tx_ready interrupt disabled
R/W
b[0] = 1 --> pck_tx_ready interrupt enabled
b[1] = 0 --> pck_received interrupt disabled
b[1] = 1 --> pck_received interrupt enabled
b[2] = 0 --> cca_ed_ready interrupt disabled
b[2] = 1 --> cca_ed_ready interrupt enabled
b[3] = 0 --> plme_ready interrupt disabled
b[3] = 1 --> plme_ready interrupt enabled
b[7:4] not used
Via this register, the internal modem interrupts can be enabled or
disabled. PLME_ready is enabled at start-up; after reset, a
PLME_ready is generated.
12
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